A Self-Reconfigurable Gate Array Architecture
نویسندگان
چکیده
This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chip configuration/data memory. These two features are necessary for efficient self-reconfiguration and are useful in general as well—no other device offers both features. The enhanced context switching feature permits arbitrary regions of the chip to selectively context switch—its not necessary for the whole device to do so. The memory access feature allows data transfer between logic cells and memory locations, and also directly between memory locations. The key innovation enabling the above features is the use of a mesh of trees based interconnect with logic cells and memory blocks at the leaf nodes and identical switches at other nodes. The mesh of trees topology allows a logic cell to be associated with a pair of switches. The logic cell and the switches can be placed close to the memory block that stores their configuration bits. The physical proximity enables fast context switching while the mesh of trees topology permits fast memory access. To evaluate the architecture, a point design with 8 8 logic cells was synthesized using a standard cell library for a 0.25 m process with 5 metal layers. Timing results obtained show that both context switching and memory access can be performed within a 10 ns clock cycle. Finally, this paper also illustrates how self-reconfiguration can be used to do basic routing operations of connecting two logic cells or inserting a logic cell by breaking an existing connection—algorithms (implemented as configured logic) to perform the above operations in a few clock cycles are presented.
منابع مشابه
Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation
In this paper, we describe organization of a machine learning system based on dynamically reconfigurable architecture and self-organization. This system learns typical neural network tasks using self-organizing learning array algorithm described elsewhere. To develop this system, we adopt hardware-software codesign approach based on combining an array of VIRTEX XCV1000 FPGAs with custom softwar...
متن کاملReconfigurable Computing A review of the technology and its architecture
Reconfigurable computing is a computer architecture which is intended to fill the gap between the hardware and the software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Most commonly and widely used high speed computing fabrics deployed in reconfigurable computing are field-programmable gate arrays (FPGAs). This pap...
متن کاملA Self-Reconfigurable Computing Platform Hardware Architecture
Field Programmable Gate Arrays (FPGAs) have recently been increasingly used for highly-parallel processing of compute intensive tasks. This paper introduces an FPGA hardware platform architecture that is PC-based, allows for fast reconfiguration over the PCI bus, and retains a simple physical hardware design. The design considerations are first discussed, then the resulting system architecture ...
متن کاملAccelerating Algorithms using a Dataflow Graph in a Reconfigurable System
In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The result...
متن کاملTag Management in a Reconfigurable Tagged-Token Dataflow Architecture
Combining dataflow concepts with reconfigurable computing provides a great potential to exploit the application parallelism efficiently. However, to express such parallelism cannot be a trivial task. Therefore, there is a great effort to automatically translate programs originally written in procedural languages (like C and Java) into dataflow architectures which express the parallelism in a na...
متن کاملAn Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms
Reconfigurable hardware is emerging as the best option for the efficient implementation of complex and computationally expensive signal processing algorithms. Reconfigurable hardware exploits the benefit of high of computational efficiency of hardware as well as flexibility of software implementation. Field Programmable Gate Array (FPGA) which finds wide range of applications in the field of si...
متن کامل